This invention relates to a ferroelectric nonvolatile memory and more particularly to a ferroelectric nonvolatile memory having ferroelectric capacitors connected to the gates of field effect transistors of MOS or MIS structure (ferroelectric-gate FET) and a readout method for reading out information from the memory.
If a junction is made between semiconductor and ferroelectrics, it is expected that states in which holes and electrons are respectively induced on the semiconductor surface depending on the polarization direction of the ferroelectrics occur. Therefore, an attempt is already made to set the above two states to correspond to xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d and form a nonvolatile memory in which the memory contents will not be erased even if the power supply is turned OFF by use of ferroelectrics for forming the gate insulating film of the MOS field effect transistor. However, a device which can be practically used is not realized up to the present time. The most important reason why it is difficult to form the device of this structure is that a necessary current will not flow between the source and drain of the field effect transistor since traps are generated at the interface to capture holes and electrons, if the semiconductor and ferroelectrics are bonded together.
In order to solve the above problem, an MFIS (M: metal or conductor, F: ferroelectrics, I: insulator, S: semiconductor) structure having a dielectric (paraelectric) film such as a silicon dioxide (SiO2) film which makes it difficult to generate interfacial traps between the ferroelectric film and the semiconductor substrate and an MFMIS structure further having a conductive film between the ferroelectric film and the dielectric film are proposed. The MFIS structure is disclosed in, for example, IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 4, APRIL 1997 pp. 160-162 TOKUMITSU et al. xe2x80x9cNonvolatile Memory Operations of Metal-Ferroelectric-Insulator-Semiconductor (MFIS) FET""s Using PLZT/STO/Si(100) Structuresxe2x80x9d and the MFMIS structure is disclosed in, for example, Jpn. J. Appl. Phys. Vol. 38 (1999) pp. 2285-2288 Part 1, No. 4B, April 1999 FUJIMORI et al. xe2x80x9cProperties of Ferroelectric Memory FET Using Sr2(Ta,Nb)2O7 Thin Filmxe2x80x9d.
However, if a laminated structure of the ferroelectric film and the dielectric film is used as the gate insulating film of the field effect transistor, new problems that (1) the programming voltage of information becomes high, (2) information holding time (data retention time) becomes short and the like occur. The problems are described in detail below.
First, the problem that the programming voltage becomes high is explained by taking a concrete structure as an example. Assume that a semiconductor substrate is composed of Si, the ferroelectric film is composed of lead titanate zirconate (PZT: Pbzr1xe2x88x92xTixO3), and the dielectric film is composed of SiO2. The same explanation may be applied to a case of the MFIS structure, but the MFMIS structure is used as the gate electrode structure to prevent mutual diffusion of Pb atoms in the PZT film and Si atoms in the SiO2 film in a case of materials used in this example. The dielectric constant of SiO2 is 3.9 and the dielectric constant of PZT is set to approx. 200 to 600 depending on the composition ratio of Zr and Ti, and the explanation is made by assuming that the dielectric constant thereof is 390 for simplicity. Further, as the general assumption, the thickness of the SiO2 film is {fraction (1/10)} of that of the PZT film.
Since the capacitance of the capacitor is proportional to the dielectric constant of the insulating film provided between the electrodes and inversely proportional to the film thickness of the insulating film, the ratio between the capacitances of the ferroelectric capacitor and the dielectric capacitor becomes 10:1. Further, when the two capacitors are connected in series and a voltage is applied thereto, voltages applied to the respective capacitors are inversely proportional to the capacitances of the capacitors, and therefore, the voltage applied to the ferroelectric capacitor is {fraction (1/10)} of the voltage applied to the dielectric capacitor, that is, {fraction (1/11)} of the whole voltage. Therefore, if the MFS structure in which the PZT film is directly deposited on the Si substrate can be formed and the polarization of the film can be reversed by application of 5V, a voltage which is as high as 55V is necessary to attain the polarization reversal when the MFMIS structure is formed with the same film thickness.
Next, the problem that the information holding time becomes short is explained with reference to the drawing. If the MFMIS structure is expressed by use of an equivalent circuit, a structure in which a ferroelectric capacitor CF and a dielectric capacitor C, are connected in series can be attained as shown in FIG. 1A. In this case, the depletion layer capacitance of the semiconductor is not considered and it is assumed that the entire portion of the semiconductor is kept at the ground potential.
Assuming that a voltage V is applied to the upper-side electrode, voltages of VF, VI are respectively applied to the capacitors CF, CI. At this time, the following equation can be attained.
VF+VI=Vxe2x80x83xe2x80x83(1)
If the charge amount appearing on both electrodes of the ferroelectric capacitor CF is xc2x1Q, the charges of xc2x1Q appear on both electrodes of the dielectric capacitor CI as shown in FIG. 1A under a condition that the total amount of charges on the connecting portion between the two capacitors CF, CI must be set to 0. Further, since the relation xe2x80x9cQ=CIVIxe2x80x9d is set in the dielectric capacitor CI, the following equation can be obtained by substituting the equation (1).
Q=CI(Vxe2x88x92VF)xe2x80x83xe2x80x83(2)
As indicated by the curve LA1 of FIG. 1B, it is known that the relation between Q and VF of the ferroelectric capacitor CF exhibits hysteresis. If the relation of the equation (2) is superposed on FIG. 1B, the straight line LA2 can be obtained as shown in FIG. 1B and intersections between the two lines indicate a voltage applied to the ferroelectrics and the amount of charges appearing on the electrode of the capacitor. The position A in FIG. 1B indicates Q and VF when a high voltage is applied in the positive direction and then the voltage is kept at V and the position B indicates Q and VF when a high voltage is applied in the negative direction and then the voltage is kept at V.
Therefore, if a high voltage is applied in the positive direction and then the voltage is returned to 0, Q and VF of the ferroelectric capacitor indicated by the position C are set and the direction of polarization and the direction of electric field are opposite to each other. That is, if information is held by returning the gate voltage to 0 after the programming operation is effected by applying a positive voltage to the gate electrode of the field effect transistor having the MFIS or MFMIS gate structure, the electric field in the opposite direction to the direction of the polarization is applied to the ferroelectrics and the remnant polarization amount disappears in a brief period of time. Particularly, when the capacitance of the dielectric capacitor serially inserted is small, the magnitude of the electric field in the opposite direction becomes closer to coercive electric field (which is required to return the polarization amount to 0) and the polarization retention time becomes extremely short.
The problem that the holding time is short cannot be neglected not only in the MFIS or MFMIS structure but also in the MFS structure in some cases. That is, the depletion layer capacitor formed on the semiconductor surface and the ferroelectric capacitor form a series-connected capacitor depending on the bias condition and substantially the same problem as that occurring as shown in FIG. 1B occurs.
Thus, in the conventional nonvolatile memory using the ferroelectrics for forming the gate insulating film of the MOS field effect transistor, it is necessary to use the MFIS or MFMIS structure so as not to generate interfacial traps between the semiconductor substrate and the ferroelectric film. However, if this type of structure is used, there occurs a problem that a voltage for programmed information becomes high and the information holding time becomes short.
Accordingly, a first object of this invention is to provide a ferroelectric nonvolatile memory having memory cell structures each including a ferroelectric capacitor and capable of lowering the information programming voltage and making the information holding time long.
Further, a second object of this invention is to provide a storage/holding method of a ferroelectric nonvolatile memory having memory cell structures each including a ferroelectric capacitor and capable of lowering the information programming voltage and making the information holding time long.
A third object of this invention is to provide a readout method for a ferroelectric nonvolatile memory capable of permitting information to be efficiently read out from a memory cell including a ferroelectric capacitor.
The first object of this invention can be attained by a ferroelectric nonvolatile memory having memory cells each for storing information by utilizing the polarization of a ferroelectric film, comprising memory cells each including a field effect transistor, a first ferroelectric capacitor having one of electrodes connected to a gate electrode of the field effect transistor, and a second ferroelectric capacitor in which one of electrodes is connected to the gate electrode of the field effect transistor and the remnant polarization amount is substantially equal to that of the first ferroelectric capacitor; wherein information is stored by polarizing thin ferroelectric films of the first and second ferroelectric capacitors in opposite directions to each other with respect to the gate electrode of the field effect transistor.
Further, the first object of this invention can be attained by a ferroelectric nonvolatile memory comprising a plurality of thin single crystal Si films formed in parallel in a stripe form on an insulating substrate, each stripe being separated in a stripe direction and having a junction structure of a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of the first conductivity type; a thin dielectric film formed to cover the thin single crystal Si films; a plurality of gate electrodes formed on the thin dielectric film to cover at least the second semiconductor regions which lie at the center of the junction structures along the stripes of the thin single crystal Si films; a thin ferroelectric film formed on the thin dielectric film and gate electrodes; a plurality of first stripe-form electrodes whose upper surfaces and side surfaces are covered with thin insulating films and which are arranged on the thin dielectric film to pass above the gate electrodes in a direction perpendicular to the stripes of the thin single crystal Si films; and a plurality of second stripe-form electrodes arranged on the thin dielectric film and first stripe-form electrodes to pass above the gate electrodes in a direction parallel to the stripes of the thin single crystal Si films; wherein an overlapping area of the first stripe-form electrode and the gate electrode is substantially equal to an area in which the second stripe-form electrode and the gate electrode overlap each other without interposing the first stripe-form electrode therebetween.
Further, the first object of this invention can be attained by a ferroelectric nonvolatile memory comprising a plurality of thin single crystal Si films formed in parallel in a stripe form on an insulating substrate, each stripe being separated in a stripe direction and having a junction structure of a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of the first conductivity type; a thin dielectric film formed to cover the thin single crystal Si films; a plurality of gate electrodes formed on the thin dielectric film to cover at least the second semiconductor regions which lie at the center of the junction structures along the stripes of the thin single crystal Si films; a first thin ferroelectric film formed on the thin dielectric film and gate electrodes; a plurality of first stripe-form electrodes arranged on the first thin dielectric film to pass above the gate electrodes in a direction perpendicular to the stripes of the thin single crystal Si films; a second thin ferroelectric film formed on the first stripe-form electrodes and gate electrodes; and a plurality of second stripe-form electrodes arranged on the second thin ferroelectric film to pass above the gate electrodes in a direction parallel to the stripes of the thin single crystal Si films; wherein an overlapping area of the first stripe-form electrode and the gate electrode is substantially equal to an area in which the second stripe-form electrode and the gate electrode overlap each other without interposing the first stripe-form electrode therebetween.
With the above construction, the two ferroelectric capacitors having substantially the same remnant polarization amount are connected to the gate electrode of the field effect transistor, forming a memory cell, and information is stored by the polarization direction and remnant polarization of the thin ferroelectric film. Further, since the thin ferroelectric films of the capacitors are polarized in opposite directions to each other with respect to the gate electrode of the transistor, at the time of storage of information, remnant polarization substantially equal charges caused by the polarization of the thin ferroelectric film are not induced on the semiconductor surface acting as the channel region of the transistor.
In this case, the information programming voltage can be lowered since the voltage is applied directly to the thin ferroelectric film. Further, the information can be held for a long time, because the internal electric fields of the two ferroelectric capacitors are 0, no matter whether the information is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. It should be noted that the information is xe2x80x9c1xe2x80x9d when the first and second ferroelectric capacitors are polarized upwards and downwards, respectively, and is xe2x80x9c0xe2x80x9d when the first and second ferroelectric capacitors are polarized downwards and upwards, respectively.
Further, the second object of this invention can be attained by a storage/holding method of a ferroelectric nonvolatile memory having memory cells each including a field effect transistor, a first ferroelectric capacitor having one of electrodes connected to a gate electrode of the field effect transistor, and a second ferroelectric capacitor in which one of electrodes is connected to the gate electrode of the field effect transistor and the remnant polarization amount is substantially equal to that of the first ferroelectric capacitor; comprising the steps of polarizing the thin ferroelectric films of the first and second ferroelectric capacitors in opposite directions to each other with respect to the gate electrode of the field effect transistor by grounding the other electrode of the second ferroelectric capacitor and applying a voltage to the other electrode of the first ferroelectric capacitor; and setting the other electrode of the first ferroelectric capacitor to 0V.
With the above method, since the voltage is directly applied to the thin ferroelectric film, the information programming voltage can be lowered. Further, the information can be held for a long time, because the internal electric fields of the two ferroelectric capacitors are 0, no matter whether the information is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. It should be noted that the information is xe2x80x9c1xe2x80x9d when the first and second ferroelectric capacitors are polarized upwards and downwards, respectively, and is xe2x80x9c0xe2x80x9d when the first and second ferroelectric capacitors are polarized downwards and upwards, respectively.
The third object of this invention can be attained by a readout method of a ferroelectric nonvolatile memory which has memory cells each including a field effect transistor, a first ferroelectric capacitor having one of electrodes connected to a gate electrode of the field effect transistor, and a second ferroelectric capacitor in which one of electrodes is connected to the gate electrode of the field effect transistor and the remnant polarization amount is substantially equal to that of the first ferroelectric capacitor and in which information is stored by polarizing the thin ferroelectric films of the first and second ferroelectric capacitors in opposite directions to each other with respect to the gate electrode of the field effect transistor, comprising the steps of setting the other electrode of the second ferroelectric capacitor into an electrically floating state; applying a positive voltage pulse to the other electrode of the first ferroelectric capacitors; and detecting a drain current in the field effect transistor to determine stored information.
Further, the third object of this invention can be attained by a readout method of a ferroelectric nonvolatile memory which has memory cells each including a field effect transistor, a first ferroelectric capacitor having one of electrodes connected to a gate electrode of the field effect transistor, and a second ferroelectric capacitor in which one of electrodes is connected to the gate electrode of the field effect transistor and the remnant polarization amount is substantially equal to that of the first ferroelectric capacitor and in which information is stored by polarizing the thin ferroelectric films of the first and second ferroelectric capacitors in opposite directions to each other with respect to the gate electrode of the field effect transistor, comprising the steps of setting the other electrode of the second ferroelectric capacitor into an electrically floating state; applying a positive voltage pulse to the other electrode of the first ferroelectric capacitor; and subsequently applying a negative voltage pulse whose absolute value is smaller than the positive voltage pulse to the other electrode of the first ferroelectric capacitor.
In the above method, the negative voltage pulse, which has a smaller absolute value than the positive voltage pulse, is applied after the positive voltage pulse is applied to the other electrode of the first ferroelectric capacitor, while the other electrode of the second ferroelectric capacitor is electrically floating to read information. The application of the negative voltage pulse is useful in suppressing the reduction of the remnant polarization, in case where the programming data is xe2x80x9c1xe2x80x9d. In this regard, it should be noted that the programming data is xe2x80x9c0xe2x80x9d when the first and second ferroelectric capacitors are polarized downwards and upwards, respectively, and is xe2x80x9c1xe2x80x9d when the first and second ferroelectric capacitors are polarized upwards and downwards, respectively.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.